PerfSuite 1.0 summary for execution of gen.ver2.3.inte (PID=9867, domain=user) Based on 800 MHz -1 GenuineIntel 0 CPU CPU revision 6.000 Event Counter Name Counter Value =================================================================== 0 Conditional branch instructions mispredicted............. 3006093956 1 Conditional branch instructions correctly predicted...... 32974709880 2 Conditional branch instructions taken.................... 26952022279 3 Floating point instructions.............................. 44525980237 4 Total cycles............................................. 353262206234 5 Instructions completed................................... 489764680025 6 Level 1 data cache accesses.............................. 56390921533 7 Level 1 data cache hits.................................. 41911206947 8 Level 1 data cache misses................................ 14615753570 9 Level 1 load misses...................................... 17611912424 10 Level 1 cache misses..................................... 17597248300 11 Level 2 data cache accesses.............................. 53158617899 12 Level 2 data cache misses................................ 8440205387 13 Level 2 data cache reads................................. 43528651785 14 Level 2 data cache writes................................ 10240563775 15 Level 2 load misses...................................... 3615923337 16 Level 2 store misses..................................... 667575973 17 Level 2 cache misses..................................... 8529931717 18 Level 3 data cache accesses.............................. 3826843278 19 Level 3 data cache hits.................................. 2799591986 20 Level 3 data cache misses................................ 999714206 21 Level 3 data cache reads................................. 3573882130 22 Level 3 data cache writes................................ 171800425 23 Level 3 load misses...................................... 944624814 24 Level 3 store misses..................................... 49427000 25 Level 3 cache misses..................................... 1024569375 26 Load instructions........................................ 84907675686 27 Load/store instructions completed........................ 95346092870 28 Cycles Stalled Waiting for memory accesses............... 140032176122 29 Store instructions....................................... 10267472354 30 Cycles with no instruction issue......................... 67247126931 31 Data translation lookaside buffer misses................. 8365029 Statistics =================================================================== Graduated instructions/cycle................................... 1.386406 Graduated floating point instructions/cycle.................... 0.126042 Graduated loads & stores/cycle................................. 0.269902 Graduated loads & stores/floating point instruction............ 2.141359 L1 Cache Line Reuse............................................ 5.523515 L2 Cache Line Reuse............................................ 0.731682 L3 Cache Line Reuse............................................ 7.442618 L1 Data Cache Hit Rate......................................... 0.846708 L2 Data Cache Hit Rate......................................... 0.422527 L3 Data Cache Hit Rate......................................... 0.881553 % cycles w/no instruction issue................................ 19.036037 % cycles waiting for memory access............................. 39.639729 Correct branch predictions/branches taken...................... 1.000000 MFLOPS......................................................... 100.833839
Figure 1: Output from the PSRUN tool of PerfSuite showing hardware events and derived metrics gathered via PAPI.