Listing 1: Defining a 32-bit add instruction for a hypothetical processor
(define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=r" (plus:SI (match_operand:SI 1 "register_operand" "%r") (match_operand:SI 2 "register_operand" "r")))] "" "add %0, %1, %2") End of Listing