Itanium 2 Developer Days Diary

Making Sense of Microarchitecture

The main difference between standard processors and the Intel Itanium 2 microprocessors is Explicitly Parallel Instruction Computing (EPIC), which shifts the responsibility for maximizing parallelism from the processor to the compiler. Unlike microprocessors employing Reduced Instruction Set Computing (RISC) or Complex Instruction Set Computing (CISC) models, in the EPIC model the compiler, aware that there are multiple execution units, groups parallel-ready instructions in bundles. The processor executes the bundles in parallel without runtime analysis.

The Intel Itanium 2 microprocessor has other speed-enhancing features in addition to the EPIC paradigm; in most cases, the compiler exploits them automatically. For example, non-EPIC processors use branch prediction to speed up processing times. Encountering a code branch, x86 chips don't wait around to find out which way to go. They "guess." Branch prediction algorithms are almost always right, but in the highly branched code relevant to data- and calculation-intensive computing, even a tiny percentage of wrong guesses can add up to big performance hits because a wrong guess sends the process back to the beginning.

The Intel Itanium 2 processor does use prediction, but adds predication to avoid misprediction performance hits by running each possible variation of a branch in parallel and tossing the incorrect result. The microprocessor actually contains extra bits which can be set to "true" or "false" for a given predicated instruction. The compiler chooses which branches are suitable for predication and sets the bit. All developers have to do is re-compile for the Intel Itanium 2 processor to make use of predication

Optimal use of the Intel Itanium 2 microarchitecture's extensive onboard memory caches is also critical to maximizing performance. "The idea is to arrange program execution so that needed instructions and data are in L1 cache as much as possible," said HP/s Dick Nicholson at the Developer Days conference sponsored by the Itanium Solutions Alliance. "In a best case/worst case comparison, a program whose data is always in Level 1 cache when needed will run much faster as a program whose data always has to be fetched from main memory."

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Figure 1: Intel Itanium 2 microarchitecture.