Multirate DSP, part 3: ADC oversampling

• Oversampling rate system
• First-order SDM with 2-bit ADC
• Sampling rate = 4MHz
• Maximum audio input frequency = 4 kHz.

Solution: Since m = 2 bits, and

f_s/(2f_max) = 4000 kHz/(2 × 4 kHz) = 500.

we calculate

n = m + 1.5 × log₂ (f_s/(2f_max)) – 0.86 = 2 + 1.5 × log₂ (500) – 0.86 ≈ 15 bits.

We can also extend the first-order SDM DSP model to the second-order SDM DSP model by cascading one section of the first-order discrete-time analog filter, as depicted in Figure 12-29.

Figure 12-29. DSP model for the second-order SDM ADC.

Similarly to the first-order SDM DSP model, applying the z-transform leads to the following relationship:

Notice that the noise shaping filter becomes a second-order highpass filter; hence, the more quantization noise is pushed to the high-frequency range, the better ADC resolution is expected to be. In a similar analysis to the first-order SDM, we get the following useful formulas:

n = m + 2.5 × log₂ (f_s/(2f_max)) – 2.14 (12.34)

(f_s/(2f_max))⁵ = (π⁴/5) × 2^{2(n – m)}. (12.35)

In general, the Kth-order SDM DSP model and ADC resolution formulas are given as:

n = m + 0.5 × (2K + 1) × log₂ (f_s/(2f_max)) – 0.5 × log₂ (π^2K/(2K + 1)) (12.37)

(f_s/(2f_max))^{(2K + 1)} = (π^2K/(2K + 1)) × 2^{2(n – m)}. (12.38)

Example 12.10.
Given the oversampling rate DSP system with the following specifications, determine the effective ADC resolution:

• Second-order SDM = 1-bit ADC
• Sampling rate = 1 MHz
• Maximum audio input frequency = 4 kHz.

Solution:

n = 1 + 2.5 × log₂ (1000 kHz/24 kHz) – 2.14 ≈ 16 bits.

Next, we review the application of the oversampling ADC used in industry. Figure 12-30 illustrates a function diagram for the MAX1402 low-power, multichannel oversampling sigma-delta analog-to-digital converter used in industry. It applies a sigma-delta modulator with a digital decimation filter to achieve 16-bit accuracy. The device offers three fully differential input channels, which can be independently programmed. It can also be configured as five pseudo-differential input channels. It comprises two chopper buffer amplifiers and a programmable gain amplifier, a DAC unit with predicted input subtracted from the analog input to acquire the differential signal, and a second-order switched-capacitor sigma-delta modulator.

(Click to enlarge)
Figure 12-30. Functional diagram for the sigma-delta ADC.

The chip produces a 1-bit data stream, which will be filtered by the integrated digital filter to complete ADC. The digital filter's user-selectable decimation factor offers flexibility for conversion resolution to be reduced in exchange for a higher data rate, or vice versa. The integrated digital lowpass filter is first-order or third-order Sinc infinite impulse response. Such a filter offers notches corresponding to its output data rate and its frequency harmonics, so it can effectively reduce the developed image noises in the frequency domain. (The Sinc filter is beyond the scope of our discussion.) The MAX1402 can provide 16-bit accuracy at 480 samples per second and 12-bit accuracy at 4,800 samples per second. The chip finds wide application in sensors and instrumentation. Its detailed features can be found in the MAX1402 data sheet (Maxim Integrated Products, 2007).