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MMX Technology Code Optimization

By Max I. Fomitchev, September 01, 1999

Max examines MMX-code optimization techniques and shows how you can achieve maximum speed on the Intel Pentium II and AMD K6-2 processors.
Sep99: MMX Technology Code Optimization

Figure 2: Transposition of the first half of an 8×8 byte block. Each row is displayed as a packed 8-byte number. Since only one unpack operation per cycle can be executed, they were intermixed with other instructions to improve parallelism. Matrix transposition cannot be done in place unless the matrix is square.

Copyright © 1999, Dr. Dobb's Journal


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