Algorithm Alley

Principles and Performance of Cryptographic Algorithms

By Bart Preneel, Vincent Rijmen, and Antoon Bosselaers

Dr. Dobb's Journal December 1998

Table 1: Performance in clock cycles per block of output and Mbits of several additive stream ciphers, hash functions, and block ciphers on a 90-MHz Pentium. All implementations are written in assembly language, and their level of optimization is comparable. Code and data are assumed to reside in the on-chip caches (except for Snefru, Tiger, and SHARK, which require more data memory than the 8 KB of the primary data cache). Only the required memory for tables is listed. Some algorithms require additional memory for storing the state and possibly the round keys.